Exactly. I was referring to that bit at the end of the article:
"In the case of Java volatiles, part of the solution is to force all reads/writes to bypass the local registers, and immediately trigger cache reads/writes instead. As soon as the data is read/written to the L1 cache, the hardware-coherency protocol takes over and provides guaranteed coherency across all global threads. Thus ensuring that if multiple threads are reading/writing to the same variable, they are all kept in sync with one another. And this is how you can achieve inter-thread coordination in as little as 1ns."
That last sentence can be pedantically true, if you look at in a very strict context. It doesn't say the variable can be returned in 1ns - but even if it did, it says the inter-thread coordination can take place in "as little as" 1ns. If a L1 cache immediately returning it's cached value for a memory address because it has the data in E or M state, that's technically a form of inter-thread coordination, just using already-coordinated state.