[tdsanchez]

I worked at Intel when the first mobile Pentiums were being developed. Back then, gate oxides were 10-12 atoms thick. That was nearly 30 years ago and feature size was 350nm or .35 micron.

Today's 3nm processes use 3 dimensional gates that have film thicknesses on the order of 5 to 8 atoms thick and the features size is smaller than the wavelength of light used to measure expose wafers' different mask reticles that rely on using light slit interference to make features smaller than the EUV wavelength of around 10nm.

To get much smaller than 1nm using these techniques is going to run into fundamental physical limits in a decade and probably that limit will be around .5nm feature size.

The next frontier in silicon will be building three dimensional chips and IBM is a pioneer in 3D stacking of CMOS gates.