[IMSAI8080]

The answer to this might be more application specific accelerators and 3D stacking. You can't afford to have all of a chip switched on at once because of the power consumption and dissipation, so you build more optimised accelerators and keep flipping between them as you encounter different pieces of code that may benefit from each accelerator. Only a fraction of the device is ever in use at once. You 3D stack the chips to get more transistors in the same space. NAND flash chips are already 3D stacked, often with 100 layers or more.

[bee_rider]

It would be cool if chiplets got to the point where, at least, an OEM… someone Dell sized… could actually differentiate themselves by mix-and-matching a group of accelerators. Bringing back consumer-visible differentiation in CPUs (other than Apple against the world) would be nice for the market I think.

[senkora]

The industry term for the idea that most of your chip is switched off at any given time is “dark silicon”.

[kzrdude]

What about silicon that's perpetually switched off because of defects and binning (Like apple's 7 core graphics offerings and so on), that's an even darker silicon?