[dfox]

ARM is a weird beast across the spectrum of RISC designs. The original ISA design is inspired by Berkley RISC (which had only two stage pipeline) and then optimized to what can be reasonably cheaply done in the silicon process used, with the hardware implementation bearing striking similarity to traditional non pipelined "CISC" designs. This design for made cheap implementation of various instructions, like four operand ALU operations or instructions that do multiple memory accesses, which are more or less unthinkable in other RISC designs designed for pipelining and 1 IPC.