[joelby37]

You're right - including 'D' in the sensitivity list is incorrect and is a good way to lead to the synthesis of latches. Sensitivity lists should only include the clock, or clock and an asynchronous reset, or if it's combinatorial logic, all signals (with no clock).

The best explanation I've seen for two and three process FSMs is that older synthesis tools weren't smart enough to infer an FSM from anything else. At least with FPGAs, it seems like the professionals are only using the single process model. Why wouldn't you? It doesn't separate related pieces of code over multiple pages and the chance for stuffing it up is reduced significantly.

Teach people to use the single process model. Teach them that two and three process FSMs exist so that they can identify and understand them, but don't waste too much time on it. Some of the textbooks I've read devote a chapter to the distinction between Mealy and Moore state machines. Time to let this one die!