[amirhirsch]

Optimization is a bit different between an FFT algorithm running on a CPU architecture versus FPGA/hardware implementation.

If you’re making a digital filter on FPGA you are going to be optimizing your structure with a DIF-FFT to produce out of order results followed by DIT-iFFT which accepts the out of order data. The arithmetic irregularities mentioned in the article about the DIF and split-radix structure don't factor in the same when you control the hardware, the complex multiply is implemented with 3muls, and 5adds and twiddles are better computed than wasting transistors to store them.