100Gbps requires expensive FPGAs because you need very fast SERDES peripherals on-die to transmit/receive the four lanes of 25Gbps to the other device (usually a QSFP28 module but you can communicate directly between two chips with just SERDES without converting to any kind of Ethernet).
Normal logic pins on FPGAs generally can’t be used to transmit or receive fast enough (not to mention some of these standards are using multi-level signalling like PAM-4 which a normal logic pin just can’t do).
100Mbps on the other hand (like this project is doing) is possible to produce, but I do wonder how likely it would be to be able to practically receive with any meaningful cable length without an analogue front-end that you find in a PHY.
Normal logic pins on FPGAs generally can’t be used to transmit or receive fast enough (not to mention some of these standards are using multi-level signalling like PAM-4 which a normal logic pin just can’t do).
100Mbps on the other hand (like this project is doing) is possible to produce, but I do wonder how likely it would be to be able to practically receive with any meaningful cable length without an analogue front-end that you find in a PHY.