[bartlettD]

This is really neat! Lots of FPGAs have MAC peripherals or IP Cores but the PHY is usually an external component.

There are some good reasons for that though, I'm not entirely sure that an FPGA can drive hard enough for a useful Ethernet PHY except for parhaps short range stuff, not sure what happens when the isolating magnetics are added.

I wish there was a good IP Core for the IP Stack though, most implmentations of IP Ethernet on FPGAs use a softcore to run the networking stack which bumps up the utilization a lot. I'm absolutely certain a basic IP layer could be done purely in HDL which would go a long way in getting Ethernet going on lower spec FPGAs.

[robomartin]

Well, in most of the hardware designs I work on you would never want to run anything from the outside world directly into an FPGA. That's a sure way to destroy a very expensive chip. Using robust purpose-built devices with internal and external protection against such things as +/- 15 kV static discharge is important for reliability and more.

[Aromasin]

Intel have Hard IP in their Stratix/Agilex parts. They've got integrated PCS and PMA in their dedicated transceiver tiles. Agilex supports 10G to 400G too.

[gorkish]

The OpenHPSDR project implements a good chunk of basic networking without a soft core at 100mbps and 1gbps; ARP, DHCP, and UDP are in there. TCP is not implemented.