[johapers]

I apologize if this is a bit long:

The answer can be found in the supplementary information to the article here: http://pubs.acs.org/doi/suppl/10.1021/nl203701g/suppl_file/n...

In short, they grew the nanotubes on a quarts crystal, transferred them with tape quite randomly to gates already made on a Si-wafer and then etched and metalized around these gates. They then tested a large amount of devices to find ones where a nanotube of the right kind (semiconducting) had placed itself in a correct alignment with the gate and metalized contacts (source and drain). Once they knew what devices were working they imaged some of the working devices with an Atomic Force Microscope (AFM) and did a bunch of standard transistor measurements.

As was commented earlier, the specific growth of nanotubes in a well defined position is not easily achieved. There is IMO a long time until anyone can do a full chip where nanotubes grow exactly where one wants the transistors. It might even be that graphene is a more convenient technology for just this reason (since graphene can be grown somewhat more conveniently by annealing SiC wafers). A side note I guess is that growing nanotubes and pillars vertically can be done in specific spots on a wafer, but that makes manufacturing of the gate a bit problematic. And I do not know wheter carbon nanotubes can be grown selectively this way.