[bradfa]

As I mentioned in another comment, 2GB is the maximum memory size that all of the processors within the SOC can access, so it's a perfectly reasonable amount of RAM to spec for this SOC.

The Cortex-A CPUs can access more than 2GB but because that memory requires more than 32 bit addressing, the other processors cannot easily access it.

This is a common theme in similar TI SOCs. For example, the AM57xx SOC which are used on the Beagle-X15 and Beagle-AI can have more memory available to the Cortex-A15 than can be possibly made available to the DSP and Cortex-M4 processors. The Cortex-A15 has a special interface to the memory controller which enables extended address use beyond 32 bits where-as the other processors and subsystems within the SOC are all attached to a bus where 32 bit addresses are the maximum.

[KMag]

> The Cortex-A CPUs can access more than 2GB but because that memory requires more than 32 bit addressing, the other processors cannot easily access it.

What's preventing the 32-bit CPUs from accessing the full 4 GB of a 32-bit address space?

[bradfa]

The main memory map places the DDR memory starting at 0x8000_0000 up to 0xffff_ffff in both AM62x and AM57xx. Below 0x8000_0000 are a bunch of other memory mapped devices and interfaces.

Additional memory beyond 2GB are all located above 0x1_0000_0000 address.