[adwn]

VHDL, for example, is case insensitive. This means that if I have a simple architecture with a single FSM, and I define a type and a signal for the FSM state like this:

    architecture impl of SimpleModule is
        type State is (Idle, Busy, Done);
        signal state: State;
    begin
        ...
    end;

I get an error message for the signal declaration, because the identifier state is already used for the type State. It's easy to fix (for example, using FsmState and fsm_state), but it's just so annoying each and every time.