[eimrine]

So why a CPU cache (L1 L2 L3) has 2 halves, one for code and another for data?

[t-3]

Can you directly choose what goes into the cache or is it just a technical optimization? Which instructions read and write the cache?

[zerohp]

You can directly choose what is available on the instruction side by using the XN (aka XD) permission bits in the page table. Other mechanisms exist to make pages readable by instruction fetch but not readable by the data side.

Von Neumann vs Harvard is a pointless discussion. Both are too simplistic describe modern architectures.