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by bippingchip
1208 days ago
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There are 2 main difference between many university (and even the much larger dedicated research lab/fabs like for example in Albany/NY Creates):
- Research labs are typically equipped to focus on critical parts of the overal production process they want to do research on. But to get actual designs manufactured you need a fully working and sufficiently yielding process from bare wafers to transistors, interconnect, passivation etc. This is easily multiple hundreds of steps to 1000+ different process steps (just think about making a single metal layer: deposit resist, expose, etch, deposit barrier, liner and and then metal, CMP) This works well for the uses cases you describe: dedicated inspection equipment or very niche small scale nano fabrication needed. But making a a fully working VLSI CMOS process needs much higher complexity and many more different process steps and equipment. Which brings me to the second point:
- Research labs typically don't care much about yield: they need sufficient amount of working devices to measure and show things are possible and publish about it, but they do not need to bring it up to reliably reproducible results. However when you make an ASIC with millions to billons of transistors and wires, you typically depend on ALL vias and ALL transistors working, not just 80-90% of them, to get a functional chip. This is a lot of hard and dedicated work, in a way it's an art, black magic almost to most: very few people and companies have the expertise to pull this off. It's not a big exaggeration to say only TSMC can do this really well. Just look at how much even Intel is struggling to get their next node out (it's been how many years of Tick Tock Tock Tock Tock.. now?) |
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