[gautamcgoel]

That study is very old and is based on long-outdated DRAM tech. I suspect that DDR5 has much lower error rates.

[Retric]

I would welcome more recent data, but I doubt we are talking about a 4 orders of magnitude change to get to /year vs /hour error rates.

[gautamcgoel]

Actually, Samsung claimed a factor of a million lower error rate in DDR5 vs DDR4 due to the on-die ECC.

Source: https://www.anandtech.com/show/16900/samsung-teases-512-gb-d...

[Retric]

> The company details a 512 GB module of DDR5 memory, running at DDR5-7200, designed for server and enterprise use.

That just shows how useful ECC memory is not that these bit flips didn’t occur.

[gautamcgoel]

If you scroll down a bit, the article shows a slide from Samsung claiming that DDR5 improves error rates by a factor of 10^6.

[Retric]

That’s a comparison with ODECC vs non ODECC memory chips not DDR5 vs DDR4.

ODECC was added because they wanted to be able to use DDR5 chips which would have had unacceptably large error rates without it. In other words that improvement is before the binning process, so they are selling chips with a vastly higher innate error rate to the point where the average DDR5 stick could actually be worse than the average DDR4 chip, it’s hard to say without large scale testing from multiple manufacturers.