[tgsovlerkhgsel]

I'm surprised access through /dev/mem happens below the caching layer. I wouldn't have even thought of that possibility. Any idea why that is?

[zerohp]

A very common usage for /dev/mem is to access a device through memory mapped IO from user space.

Cacheable accesses would break that use case.

[righttoolforjob]

If my memory serves me correctly you can control the mapped caching attributes using file flags, like O_SYNC, etc. Might also be architecture dependent. If you want to manipulate a memory-mapped device then you don't want caching, but if you want to see memory the same way a typical application does, then you want to keep the caching attributes in your mapping. It's a low-level tool, so there is no right or wrong really.

[ilyt]

...it's memory. Where would you cache memory access, in other memory ?

CPU got cache for caching memory

[tgsovlerkhgsel]

Exactly - the article says "the memory might be cached by the CPU which possibly incurs cache coherence problem".

I would expect the memory access to happen through the CPU and its cache, avoiding such problems.