[fathyb]

> 1 Processor, 1 Core, 4 Threads

Any idea why StarFive went with this choice for an SBC? I remember POWER7 also having 4 SMT, but it felt right for a superscalar multi-core CPU.

[rwmj]

The link in the GP comment is wrong - both SoCs have 4 cores, each with a single thread.

The reason why this SoC is faster than HiFive Unmatched seems to be down to architectural improvements.

[snvzz]

They both use U74, but different versions.

The one in JH7110 is the 2021Q1 version, AIUI.

Besides faster, it also added B extension.

[zu2_]

No. VisionFive2's RISC-V CPU does not have the B extension. I confirmed it on the actual device.

$ cat /proc/cpuinfo processor : 0 hart : 2 isa : rv64imafdc mmu : sv39 uarch : sifive,u74-mc

[snvzz]

As you say this, I realize I can't find anywhere that it does.

I do not know why I thought it did. Possibly as U74-MC[0] supports that option.

Interestingly, I also took a look at RVA22[1], and found it requires Zbb but not the whole B.

Your /proc/cpuinfo isn't listing Z* extensions. Maybe lscpu output would be more detailed?

0. https://www.sifive.com/cores/u74-mc

1. https://github.com/riscv/riscv-profiles/blob/main/profiles.a...

[zu2_]

Oh, I was mistaken. I've verified that at least the rev instruction works (tested on clang -march=rv64imafdcb0p94).

[snvzz]

It is quite possible it implements some B instructions (like the Za or Zb extensions) but not B as a whole.

[snvzz]

Got mine.

OpenSBI says:

Boot HART Base ISA : rv64imafdcbx

[fathyb]

Ah, makes much more sense. Thanks!

[psychphysic]

Embarrassingly I thought I had a Quad-Core based on `lscpu`.

I have been meaning to make use of it but so far just as a vnc server which works well loading XFCE on the minimal desktop image.

Edit: can see below that it is indeed a quad core... Embarrassed I took an internet strangers off the cuff remark as gospel

[snvzz]

It gets more complicated :D

Quad-core 64-bit RISC-V SiFive U74 (RV64GC) processor @ up to 1.5 GHz with 32KB D-Cache, 32KB I-cache

Single-core 64-bit RISC-V SiFive S7 (RV64IMAC) monitor core with 16KB I-cache, 8KB DTIM

Single-core 32-bit RISC-V SiFive E24 (RV32IMFC) real-time control core with 16KB I-cache

[photonbeam]

It has 4 cores with 1 thread each, rather than 1 core with 4 thread