[phoehne]

There are 2 flavors of the ESP, depending on model. The Xtensa cores and RISCV, go with the RISCV variant. The Xtensa variant requires you to use their compilers, which are derived from he ones provided by Cadence. There's a better path long-term for the RISCV cores to get tooling on par to what's available for ARM.

[jononor]

The Xtensa based ESP32 chips have upstream support in GCC, do they not?

[phoehne]

Espressif has compilers you can download. GCC may work fine, but I’d use their compilers.

[brocklobsta]

Yes, but not llvm support. Which makes rust a no go.

[steveklabnik]

Upstream support landed a couple of weeks ago: https://github.com/llvm/llvm-project/search?o=desc&p=1&q=Xte...

Rust support landed before that, https://github.com/esp-rs

This is all being done by Xtensa themselves, including the Rust.