Maybe! One main challenge is the (at least) six-way local intertile communications. The T2s use BeagleBone Greens, which have two PRUs that I slice three ways each to do packet transfers. The RP2040 anyway has two 'PIO' instances that seem similar.
But I'm unsure that any redo at that scale would improve delivered performance that much.
If I had it to do over I think I'd've tried to put an ethernet router chip on each tile and basically do backplane ethernet between tiles.
But I dream of LVDS serdes between tiles with low-level packet stuff handled in FPGA fabric..
But I'm unsure that any redo at that scale would improve delivered performance that much.
If I had it to do over I think I'd've tried to put an ethernet router chip on each tile and basically do backplane ethernet between tiles.
But I dream of LVDS serdes between tiles with low-level packet stuff handled in FPGA fabric..