[somat]

vhdl started as a project to document integrated circuits. The department of defense was getting a lot, and more complicated, integrated circuits and wanted a standard to document the functionality. At some point someone thought, "you know, if the documentation is good enough we could reverse it and synthesize a circuit from it", and thus why you use vhdl(or more likely verilog) to program your fpga.

The two languages fill the same role in the ecosystem, I have to say that I have never used ether, but my impression is that vhdl has clearer syntax(if you can stomach it's ada look and feel) and verilog has better tooling. which makes sense considering that one was a documentation project and the other was an internal tool for simulation that escaped into the wild.