[VLM]

Apparently simulated.

You can see in the UART code for example:

https://github.com/nyuichi/GAIA3/blob/master/hardware/Rx.vhd

file input_file : ft open READ_MODE is input_filename;

read(input_file, c);

data <= std_logic_vector(to_unsigned(character'pos(c), 8));

And so on and so forth, to pump a file on the simulation PC into a VHDL logic array one byte at a time as a simulation of a UART.

Would be pretty funny if the above is the "wrong" repo for the story, but it is at least "an implementation" of the GAIA architecture, if not "the implementation" from the story.