[posix_compliant]

I’m confused by the cache graphs: it looks like the direct-mapped cache has multiple lines drawn from a single cache line to different blocks in main memory.

From what I understand, a hardware cache wouldn’t store a line multiple times in main memory.

[opencl]

The direct mapped cache graph is just showing that each cache line is mapped to multiple addresses.

So in that direct mapped example blocks 0, 64, and 256 are all mapped to cache line 0, and you can only have one of them in cache at any given moment. If block 0 is in cache and block 256 gets accessed, block 0 will be evicted from cache because block 256 will replace it in cache line 0.

[posix_compliant]

I see. I was interpreting the line as “is stored in the cache from” when it really means “can be stored in the cache at”. Using directed arrows might help some. Thanks!

[CrazyStat]

A connecting line there means that that the data from that memory location can be stored in that cache line. In the fully associative cache any memory location can use any cache line. In the direct-mapped cache each memory location has one designated cache line it must use (but each cache line has multiple main memory locations associated with it).

[flumpcakes]

This has been a very helpful and explained very clearly and directly. Thank you. I'm having trouble keeping up with some of the comments in this thread but this one has been very illuminating.