[abiloe]

> Mostly everyone else seems to define the bitness of CPUs by their capacity to add numbers in one go, not by the address space they can address.

Nah, only historically. Yes, "8-bit" refers to the ALU. Back in the day, 16-bit was similar. But even then it was muddy, because when talking about operating systems like Unix or NT the key question about bitness would be in the context of a 32-bit flat addressing model, not really the data width.

By the time the 64-bit era rolled around, the "64-bits" definitely referred to address space.. The original Pentium had a 64-bit data path and had instructions (MMX, eg PADDQ) that could operate on 64-bit numbers - no one would call it 64-bit. By the early 2000s with the big push to mainstreaming 64-bit, it was all breaking out of the 4GB address space limitation - not the width of data.

> define the bitness of CPUs by their capacity to add numbers in one go

This is nebulous and therefore troublesome to define. Are we talking about the ISA or the internal circuitry (ALU and/or data path)? Is the 68000 a 16-bit or 32-bit CPU?

[sparkie]

> By the time the 64-bit era rolled around, the "64-bits" definitely referred to address space.. The original Pentium had a 64-bit data path and had instructions (MMX, eg PADDQ) that could operate on 64-bit numbers - no one would call it 64-bit. By the early 2000s with the big push to mainstreaming 64-bit, it was all breaking out of the 4GB address space limitation - not the width of data.

We're ~20 years down the line and none of these "64-bit" processors support 64-bit addressing yet. Most support up to 48-bits of addressing, with some newer intel chips supporting 57-bit addresses with 5-level paging.

I always took the bit-ness of the processor to refer to the data bus size between the cpu and main memory, aka, the size of a machine word.

[flohofwoe]

> Yes, "8-bit" refers to the ALU.

By that definition, the Z80 would be a 4-bit CPU ;)

https://www.righto.com/2013/09/the-z-80-has-4-bit-alu-heres-...

...but if you take the data bus width, then the 8088 would be an 8-bit CPU, which isn't quite right either...

But you also can't take the address bus width, because modern "64-bit" CPUs can't actually address 64 bits of physical memory...

I think it's best to treat the 'bit-ness' of a CPU or computer system purely as a marketing term.

[KingOfCoders]

You're right. Having written quite some Z80 code and 68k code, I need to think about this. This is decades in the past, I think outside of demo code I often used move.l in 68k so it would be a 32bit CPU to me, but seldom used double registers on the Z80 so it feels like an 8bit CPU. Perhaps that was one of the reasons the jump from the Z80 to the 68k felt so huge (perhaps it was the number and flexibility of registers). That said, "Z80 assembly language subroutines" is my most precious computer book still, the one I would take through the apocalypse.

[brucehoult]

There's not much to think about. Bitness refers to the ISA, not the implementation. It's about what registers there are and what operations on them. It is what the programmer can write.

All CPUs that execute the same programs (in their native mode) are the same bitness. This is fundamental.

If a 68040 is 32 bit then so are the 68000 and 68008.

Most of the so-called "8 bit" CPUs weren't really. They were mixed 8/16 bit. Especially something like the z80 which had a lot of 16 bit registers, could do 16 bit adds and loads and stores. But not 16 bit compares or moves in the registers (needed two 8 bit moves). But even the 6800 and 6502 had certain 16 bit operations to support the 16 bit address space. The 6809 was even more 16 bit in being able to do 16 bit moves and subtracts and compares -- other than the lack of segment registers it was very very similar to the 16 bit 8088.

One problem with the terminology is that those early microprocessor instruction sets weren't Instruction Set Architectures. There was only ever one implementation of them, so people (including their manufacturers) tended to conflate implementation details and instruction set details.