[aargh_aargh]

For dummies like me who didn't know what a chiplet is:

https://en.wikipedia.org/wiki/Chiplet

This seems to be about the third reason listed:

> Known good die (KGD): chiplets can be tested before assembly, improving the yield of the final device

Problem:

  > In general, a killer defect is defined as a defect that is 20% the size of the fabrication node.  For
  > example, a defect that is less than 9nm may be acceptable for the 45nm fabrication node, but a defect
  > larger than 2.8nm would be defined as a “killer” defect for the 14nm fabrication node.  For the 5nm
  > fabrication node, a defect measuring only 1nm could be a killer.
  > 
  > This is one of the primary reasons that it has become increasingly difficult to yield large monolithic
  > ICs (as measured in die area) when using leading edge fabrication process technology

Solution: I understood it from the visual explanation in the first chip image (AMDArt2 png) and its description in this article:

https://www.nextplatform.com/2021/06/09/amd-on-why-chiplets-...

[nordsieck]

The issue that you seem to be skirting around but not mentioning is, the chance a chip has a defect increases with die area since defects are randomly distributed across the surface of the wafer. Chiplets are a way for manufacturers to practically increase die area while keeping yields high.

[hedgehog]

In case it's not obvious the implication is that cost per good part starts to go up quickly. The wafer size and cost is essentially fixed so bigger dies mean both a lower % of parts are good and also fewer fit on the wafer in the first place. Wrong kind of hockey stick chart.

[tyingq]

AMD's EPYC-Rome processor, helpful to look at after looking at your link, as the chiplets are nice and visible:

https://cdn.wccftech.com/wp-content/uploads/2018/11/AMD-EPYC...

[londons_explore]

Is silicon manufacturing done entirely in a vacuum yet?

Because a vacuum pretty eliminates dust - with no air, dust just falls towards either the ground (if it is uncharged), or towards a positive or negatively charged surface (if the dust particle itself is charged).

[rcxdude]

No (at least not entirely: some steps are done in a vacuum or very low pressure), in part because it's harder to get a vacuum than clean enough air. Also it would cause a lot of other problems as well as not solving the whole problem: a lot of processing steps involve applying chemicals to the surface of the wafer, washing off those chemicals, or otherwise handling liquids which would boil in a vacuum. Those chemicals (including just plain water), also carry the same risk of introducing 'killer particles', so they are also a big part of the process control needed in a fab (the levels of contaminants in water that is required on modern process nodes is actually lower than can be detected practically with current technology: the last levels of water purification are effectively done blind, with yield as the only feedback mechanism).

[nsteel]

Search "tsmc contamination" for real-life examples although don't expect any details. I'm sure it's not just TSMC but it's the best place to start.