| >sadly this partly applies to RISC-V too. Not in any way that has any relevance. >Not as big of a problem as on x86, but still a fundamental limitation. Huge understatement. Instructions being any size 1-16 (x86) vs being either 16bit or 32bit long (RISC-V). As with everything else in RISC-V, the architects did the weighting, and found that the advantage in code size overwhelms the (negligible by design) added decoding cost, for anything but the tiniest of implementations (no on-die cache + no builtin ROM). As it turns out, it would be difficult to even find a use for such a core, but in any event it is still possible to make one such very specialized chip, and simply not use the C extension. Such a use would be deeply embedded, and the vendor would be in control of the full stack so there would be no concerns of compatibility with e.g. mainstream Linux distributions. They would still get ecosystem benefits; they'd be able to use the open source toolchains, as they support even naked RV32E with no extensions. |