[foft]

I'll try to answer this, though my direct experience is only with Cyclone and Max 10.

The Mister uses the Cyclone V 5CSEBA6U23I7 built on TSMC 28nm. It has 110000 logic elements and also a hard ARM.

These are on Intel 7, so there a significant process improvement.

The smallest Agilex D has the same number of logic elements(1) and the largest has 6x as many (2). Note that Agilex tends to be much more expensive than Cyclone.

Realistic maximum clock rates on the Cyclone V are 50-200MHz, depending on the length of the combinational logic chains. For the Agilex I think that it is more like peak 600MHz. So I would guess say 25% faster and say peak 750MHz?

As to fitting all the logic for n64/PS2, I don't know!

1) Comparing these directly is not quite accurate.

2) https://www.intel.com/content/www/us/en/products/docs/progra...

[dtx1]

Wow thanks. So for the Agilex D the answer is maybe, since the currently limiting factor seems to be number of logic elements and it would need at least a 3x upgrade in that regard [1] for n64. Well, one can hope that these become cheap enough for that.

[1] https://misterfpga.org/viewtopic.php?t=4535

[aseipp]

You can in theory clock the Agilex/S10 parts up-to 1GHz, but something like 600-700MHz sounds more realistic, yes. (Note that this is in the same ballpark as what Virtex UltraScale+ can do too.)

Also, regarding point 1 -- and I'm sure you know this already, but this is for everyone else -- you have to be careful when talking about "Logic Elements" with most of the industry because, even when describing 6-LUT parts, Intel/Xilinx often list "Logic Element Count" to mean "Number of logic elements when considered on a normalized 4-LUT basis." Both Intel and Xilinx do this and I guess it kind of makes sense; only their highest end parts are non-4LUTs so they're the odd ones out when compared to everything else in the industry. So when you read "Number of LEs", they normalize it to 4-LUTs since that's what your competitors (or older parts) would use, when accounting for density.

For example I have a Stratix 10 card in my server that has "Millions of logic elements" when you look at the product tables, but that is taken on a normalized 4-LUT basis. There are actually "only" about 900,000 ALMs on the device, with each ALM being 8-input and fracturable. So TL;DR the numbers between the low-end Agilex-D part and the Cyclone part is maybe not that far off.

[FullyFunctional]

100%. For the record, the metrics I care about, and the first I seek out, is blockram cycle time and total device memory capacity. Unfortunately, unlike say Xilix/AMD, Intel doesn't publish that number directly, but Xilix/AMD's fastest for is > 800 MHz for the lovely Artix US+ and it has loads of memory.

The LUT count is a murky beast beast as you realistically cannot use them all lest P&R times shall be counted in weeks.

[nfin]

did you really mean 25% faster or 4x faster?

If you really meant 25% you probably were not reffering to the clock speed/MHz, what were referring to?

[foft]

I did mean 25% faster, though it was a guesstimate. That was comparing Agilex to Agilex D, not Cyclone V to Agilex D.

FPGA logic in simple terms consists of LUTs (look up tables, used to implement gates) and registers. The LUTs can be chained several times until they connect to a register. Registers are clocked at a frequency.

Now the max frequency is calculated using the maximum time from a register output, through a bunch of LUTs to reach another register. So it depends how long the chain is.

Its more complex than that in reality since there is also the time for the clock to propagate and to route the signals around. Fortunately the software takes care of that.

I don't really know how maximum frequency is specified in the specs, but I guess it'd be something like an ideal register->single LUT->register without much routing.

[Dracophoenix]

Would a Xilinx-based equivalent to MiSTer hardware have a better price-to-performance ratio?