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by jeffbee
1371 days ago
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Fails to build from source with Rust 1.59 so I tried the C++ `c2clat` from elsewhere in the thread. Quite interesting on Alder Lake, because the quartet of Atom cores has uniform latency (they share an L2 cache and other resources) while the core-to-core latency of the Core side of the CPU varies. Note that the way these are logically numbers is 0,1 are SMT threads of the first core and so forth through 14-15. 16-19 are Atom cores with 1 thread each. CPU 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
0 0 12 60 44 60 44 60 43 50 47 56 48 58 49 60 50 79 79 78 79
1 12 0 45 45 44 44 60 43 51 49 55 47 57 49 56 51 76 76 76 76
2 60 45 0 13 42 43 53 43 48 37 52 41 53 42 53 42 72 72 72 72
3 44 45 13 0 42 43 53 42 47 37 51 40 53 41 53 42 72 72 72 72
4 60 44 42 42 0 13 56 43 49 52 54 41 56 42 42 41 75 75 74 75
5 44 44 43 43 13 0 56 43 51 54 55 41 56 42 56 42 77 77 77 77
6 60 60 53 53 56 56 0 13 49 54 56 41 57 42 57 42 78 78 78 78
7 43 43 43 42 43 43 13 0 46 47 54 41 41 41 55 41 72 71 71 71
8 50 51 48 47 49 51 49 46 0 12 51 51 54 56 55 56 75 75 75 75
9 47 49 37 37 52 54 54 47 12 0 49 53 54 56 55 54 74 69 67 68
10 56 55 52 51 54 55 56 54 51 49 0 13 53 58 56 59 75 75 76 75
11 48 47 41 40 41 41 41 41 51 53 13 0 51 52 55 59 75 75 75 75
12 58 57 53 53 56 56 57 41 54 54 53 51 0 13 55 60 77 77 77 77
13 49 49 42 41 42 42 42 41 56 56 58 52 13 0 55 54 77 77 77 77
14 60 56 53 53 42 56 57 55 55 55 56 55 55 55 0 12 74 70 78 78
15 50 51 42 42 41 42 42 41 56 54 59 59 60 54 12 0 75 74 74 77
16 79 76 72 72 75 77 78 72 75 74 75 75 77 77 74 75 0 55 55 55
17 79 76 72 72 75 77 78 71 75 69 75 75 77 77 70 74 55 0 55 55
18 78 76 72 72 74 77 78 71 75 67 76 75 77 77 78 74 55 55 0 55
19 79 76 72 72 75 77 78 71 75 68 75 75 77 77 78 77 55 55 55 0
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