1. The only thing I know about CPU Caches is associativity, which is implemented with help of tags. Tags can be whatever size the CPU designer desired, 6-bits, 9-bits, 12-bits.
2. There are other physical issues involved: fan-in, fan-out. Basically, the amount of things a wire can support is finite, limited by the amount of electricity later components use. While not the focus of CPU design, physical issues like this are likely still an issue (while they're probably fully abstracted out by the time you reach webpage caches).
3. CPU caches are organized very differently. Cache lines in particular mean that CPUs really access RAM in 64-byte blocks.
1. The only thing I know about CPU Caches is associativity, which is implemented with help of tags. Tags can be whatever size the CPU designer desired, 6-bits, 9-bits, 12-bits.
2. There are other physical issues involved: fan-in, fan-out. Basically, the amount of things a wire can support is finite, limited by the amount of electricity later components use. While not the focus of CPU design, physical issues like this are likely still an issue (while they're probably fully abstracted out by the time you reach webpage caches).
3. CPU caches are organized very differently. Cache lines in particular mean that CPUs really access RAM in 64-byte blocks.