[mattst88]

I remember reading an article about the iAPX 432 that went into extensive detail about the compounding effects of the design—I recall it describing how an operation with an small constant operand would be slow because the ISA didn't support immediates, and as a result you'd have to load it from memory, and there was not even a cache to help with that.

Does anyone know this article? I've searched and haven't been able to find it, and it was definitely worth a read.

[kps]

> the ISA didn't support immediates

I don't know the article, but have a related story. In the '90s I worked for a custom compiler shop, and a company you've heard of (not Intel) came to us with a system they wanted tools for. They had gone all-in on RISC — operations were all register-to-register, and the only memory addressing was register indirect (i.e. through an address in a register). We had to point out that it would be rather difficult to get an address into a register in the first place.

[andrewf]

Could you do it with shifts and increments? Constant loads would look just like multiplies, a glorious RISC apotheosis..

[kps]

Yes, you could get 0 by subtracting (or xoring) a register with itself, then -1 by complementing, then 1 by negating, then adding to itself to get any single bit. Then synthesize any constant by adding those. The code would be impractically slow and large, though.

[twoodfin]

I think you want “Performance Effects of Architectural Complexity in the Intel 432”

https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.14...

[linksnapzz]

I think I've read the same article, and also wish I had the reference-I do remember that there were no or few registers, and reads were from memory almost all the time..

Also-does anyone know of a an actual system that shipped with a 432? Like, manufacturer and model #?

[auroralimon]

no. i seem to recall only intel had a board in an S100(?) chassis? i think that’s the one i had access to.

[mattst88]

bcantrill linked to it separately in the comments: http://dtrace.org/blogs/bmc/2008/07/18/revisiting-the-intel-...

The particular parts I was recalling are:

> The upshot of these decisions is that you have more code (because you have no immediates) accessing more memory (because you have no registers) that is dog-slow (because you have no data cache) that itself is not cached (because you have no instruction cache). Yee haw!

Awesome.

[auroralimon]

i have it’s programmers guide around here somewhere.

[Lammy]

Could it be https://homes.cs.washington.edu/~levy/capabook/Chapter9.pdf ?

Sorry for huge quote, but it's from a huge article:

=======================================================

From section 9.2, Segments and Objects:

> All objects are addressed through capabilities which, on the Intel 432, are called accessdescriptors (ADS). (The vendor’s terminology is used in this chapter for compatibility with Intel literature. The notation “AD” is used throughout for “capability.“)

> At the lowest level, objects are composed of memory segments, and a memory segment is the most fundamental object (called a generic object on the Intel 432). Each Intel 432 segment has two parts: a data part for scalars and an accesspart for ADS, as shown in Figure 9-2. Objects requiring both data and access descriptors can be stored in a single segment. Segments are addressed through ADS, as the figure illustrates. The data part grows upward (in the positive direction) from the boundary between the two parts, while the accesspart grows downward (in the negative direction) from the dividing line. The hardware ensures that only data operations are performed on the data part and that AD operations are performed on the accesspart.

=======================================================

From section 9.4.3, Instruction Operand Addressing:

> At any moment during a procedure’s execution, ADS specified by instructions must be located in one of four environment objects. Environment object 0 is the context object itself. Instructions can specify any of the ADS within the context object’s accesspart; for example, to refer to the domain or the constants data segment. The three remaining environments, environments 1 through 3, are defined dynamically by the procedure.

> Instruction objects contain only a data part. Because Intel 432 instructions are bit-addressable and can start on arbitrary bit boundaries, instructions are addressed as bit offsets into instruction objects. The first instruction in each instruction object begins at bit displacement 64, following the header of four 16-bit predefined fields. The maximum size of an instruction segment is 64K bits, or 8K bytes, due to the bit addressing. Although there is generally one instruction object for each procedure in the domain, procedures larger than 8K bytes require additional instruction objects. The BRANCH INTERSEGMENT instruction can be used to transfer control to another instruction object within the same domain.

> The four environment segments thus provide efficient addressing of ADS. An instruction can specify an immediate 4- or g-bit access selector describing the location of an AD for an operand. Or, it can specify the location of a 16-bit accessselector located in memory or on the stack. The short direct format efficiently addresses any of the first four ADS in any of the four environments. This includes the ADS for the global constants, context message (calling parameters), and current domain within the current context. All of the processor-defined ADS within the context object’s accesspart can be addressed using an 8-bit accessselector.

=======================================================

Unrelated, but I love how they went for the "As Above, So Below" approach for growing the data-vs-access-parts of instruction object memory ^