[jhallenworld]

But balanced against basically unlimited flash size. Many of my projects end up having an external SPI-flash for one reason or another anyway.

Another similar chip is the i.MX rt1020 from NXP (except Cortex-M7 and way more expensive). The one gotcha was that there was only one QSPI-flash controller even though there were two ports. It meant that the extra port (which we assumed would be available during architecture) was not fully usable without interfering with the firmware.

[the__alchemist]

You can still get that with chips that have onboard flash, via QSPI or OctoSPI.

[dmitrygr]

> Many of my projects end up having an external SPI-flash for one reason or another anyway.

for what? What sort of possible thing would you need to do on a c-m0 that needs more than 128K of CODE!?

[jhallenworld]

Not so much for code, but lots of use for persistent data (logs, databases, etc.). Only a part of it would be used for XIP. Also with more flash space it's easy to have multiple banks for safe firmware update and the like.

[dmitrygr]

> logs, databases

in NOR flash???

:cringe:

[jhallenworld]

NOR is more durable than NAND (but smaller, more expensive per bit), but yes you have to be careful with logs. In most recent case, it was in the 10s of small records per day.

[kragen]

Wait, wasn't there some guy who got an entire Linux system booting on a microcontroller that's smaller than a Cortex-M0? https://dmitry.gr/?r=05.Projects&proj=07.%20Linux%20on%208bi...

[dmitrygr]

Yup, I did. that’s why I ask

[HeyLaughingBoy]

The libraries you pull in can be big. Add, e.g., LWIP for internet, USB filesystem management (data logging and USB firmware update), code to properly manage OTA or Ethernet updates, text strings, especially in multiple languages, etc.

What seems like a huge amount of Flash disappears quickly.

[lnsru]

ADC calibration data. Plus some ID data. Plus log of very nasty events specific to my application. And there comes external SPI flash.