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by YakBizzarro
1436 days ago
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well, depends how you define lucky. at cryogenic temperature, the leakage current of a transistor is so small that you virtually don't require DRAM refresh. I tested DRAM cells with discharge times of hours, and the transistor was not at all optimized. See https://www.rambus.com/blogs/part-1-dram-goes-cryogenic/ (not my work) |
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