Did you throw RTL at a layout engine and let it figure it out? Pretty damn close to automated and could get to automated with a little upfront elbow grease by a company specializing in such things.
Heavy analog design? It's going to be a lot more work.
Maybe my intuition is completely wrong here, but would the analog case be simplified if the target node+technology was chosen to have trace widths exactly 1/2 the size of the node being transitioned from?
I.e. the traces would have essentially the same standing-wave tuning requirements when modelled as waveguides; would catch a harmonic of the original frequency when acting as antennae; etc.
Analog isn't just RF; PHYs for weird protocols is a giant component of the space, as well as power monitoring/management. The changes in how voltage/resistance/capacitance/etc work at each node for a given layout is the heavy lift.
Additionally, you very, very rarely have the antenna on chip, and the analog bits even for RF are more signal conditioning that isn't typically modeled like waveguides, but instead more like those old analog plug board computers, simply integrated onto a chip.
> Additionally, you very, very rarely have the antenna on chip
I didn't mean that there would be components intentionally serving as antennae in a design; more that you might be choosing analog trace lengths in e.g. a modem, or SDR ADC, to minimize harmful analog-domain interference at your bus frequency — i.e. to increase SNR, you're trying to make your traces be as little like an antenna as possible for the frequency bands they're carrying signal in, because you can't just band-pass that interference away.
The nice thing about shrinking by half, in such deigns — I would think — is that if you've already "tuned" your trace paths to a quiet band (for the country the component is being licensed in), then the harmonic frequencies of that band will also be quiet. Otherwise the band's fundamental frequency wouldn't be considered quiet!
(See also: why the unlicensed commercial-use spectrum was allocated to 2.4GHz, and then to 5GHz. 2.4GHz is an obvious choice, already useless for long-range communication due to water in the atmosphere; the other is its equally-useless first harmonic. But the great thing about choosing the first harmonic in particular, is that transmitting at 5GHz isn't putting short-range harmonic noise onto any lower bands that weren't already noisy due to existing commercial use of the fundamental frequency; so you won't suddenly find your other-band devices working worse in the presence of 5GHz transmitters than they already worked due to 2.4GHz transmitters.)
> I didn't mean that there would be components intentionally serving as antennae in a design
Not an antenna per se, but RF ICs often contain silicon inductors tuned for the operating frequency of the transceiver. Shrinking those down would retune the circuit for a higher frequency.
It's not the traces that are the issue but the transistors and resistors. As h_fe goes up new parasitic modes have to be limited. Resistor geometry changes as do the values. Ratiometric design helps but isn't a panacea. And for something like low noise or complex exotic devices you might not even be able to make them with the passes in the new process.
You'd have to ask a fab probably to get real numbers, but the chips that people care about that haven't migrated to a newer node trend towards having at least some mixed analog components more than the set of all chips being made. Otherwise a shrink probably would have already made sense since 28nm isn't even the cheapest node gate for gate but already a bit chonky. It gets cheaper with even smaller nodes.
Depending on the clock frequency of the chip, a change in the length of signal carrying lines (i.e. from one gate to the next) can already result in a phase/timing shift that ruins the circuit.
It is not uncommon to have data lanes that are longer than necessary, just to keep signals on different lines in sync.
Even if you ignore all the other complications when switching nodes (and there are a LOT!), this alone prevents simple downscaling of circuits.
It is very likely that after downscaling at least part of the interconnects have to be rerouted.
As for automation of that task: It's the traveling salesman problem in disguise.
Which means that you CAN automate it, and there exists software for that purpose, but the result are hardly optimal, and most likely leave quite a lot of possible performance on the table.
Add to that all the other necessary changes when switching nodes, and it becomes fairly obvious that switching nodes, even if only porting 1:1, is a massive effort that can easily span YEARS.
The FinFET transition was a bit later than you remember: Intel switched at 22nm, TSMC at 16nm. TSMC's 28nm wasn't their last planar transistor node, but it's a sweet spot of performance vs cost.
Did you throw RTL at a layout engine and let it figure it out? Pretty damn close to automated and could get to automated with a little upfront elbow grease by a company specializing in such things.
Heavy analog design? It's going to be a lot more work.