[ajross]

Overall a good article. Though it's got this whopper:

A DRAM package is then stacked on top of the SoC. Avoiding having to route high-speed DRAM lines on the PCB itself not only saves space but it further reduces memory latency.

Uh... come again? DRAM latency is a function of the analog circuit inside the chip, not the wires you connect to it. At best, you might be able to drive the chips at a higher transfer frequency (but even then, the limit is probably on-package in the DRAM, not due to board trace problems). But that has at best a minimal effect on latency (you're shrinking the handful of transfer cycles at the end of the read).

The advantage of the PoP configuration is precisely that it saves space -- quite a bit of space, and it's a great trick. But this bit is just way off.