|
|
|
|
|
by dredmorbius
1466 days ago
|
|
To expand on this: if you're designing / building / assembling a computer or cluster, and components are 6" apart, then the minimum latency for communicating between those components is 1 nanosecond. Given clock speeds of multiple GHz, that means spending an entire clock cycle or more simply communicating between components. See also the case of the 500 mile email: https://www.ibiblio.org/harris/500milemail.html (A Sendmail misconfiguration resulted in a maximum response time of 3 milliseconds, or roughly 500 miles of travel at the speed of light. The observed behaviour was that a uni campus computer could send email only within a 500 mile radius, as noted by the statistics department.) |
|
Yeah that's expected isn't it? That's why we have caches on die. Nobody is out there expecting main memory reads to retire in a clock cycle, let alone IO! I don't think even lower tier cache access retires in a single clock cycles. That's just not how processors work these days.