[IcePic]

For RISC ISAs like MIPS, then you can do a lot of

ADD Reg0 to Reg0 and store result in Rx

OR Reg0 with reg0 and store result in Rx

XOR Reg0 with reg0 and ..

The only issue is that for RISC, all these instructions are of equal length, so flipping them around would gain you very little, or more likely zero effect unless you are chasing some corner case thing like "XOR instruction value compresses slightly better than ADD because.."