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by conradev
1472 days ago
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The author plans on using this feature to help bridge the interrupt controller: “There’s an somewhat obscure feature on M1 (and M1 Pro/Max/Ultra, henceforth referred to as M1 v2) chips where part of the GICv3 can be virtualized to guest OSes to enable faster interrupt handling.” Seemingly implementing it in a hypervisor? |
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