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by tadfisher
1490 days ago
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This is a bit hyperbolic. Intel implemented a known and popular algorithm (SRT [1]) with a standard LUT for the bit patterns expected in IEEE754 FP numbers. They were not the first, last, or only microprocessor design firm to do so. A fault in a script that copied the LUT values to the machines that program the PLAs as part of the manufacturing process led to 5 missing values in the LUT (set to 0), out of 1066 entries. There's a great writeup with the results of Intel's internal investigation [2], which outlines the challenge in testing production chips for this sort of bug. A key point: > The fraction of the total input number space that is prone to failure is 1.14 x 10^-10. So around 1 in 9 billion possible numerator/denominator pairs exhibit the bug. Testing 9 billion double-precision FDIV divides on a 60MHz Pentium would take almost four days, if my math checks out and the CPU could do 2.5 billion divides per 24 hours. [1]: https://en.wikipedia.org/wiki/Division_algorithm#SRT_divisio... [2]: https://users.fmi.uni-jena.de/~nez/rechnerarithmetik_5/fdiv_... |
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I'm aware of most of those details as I took a keen interest in the matter at the time. I'm also aware of the argument for the use of said algorithm.
Whether one adopts this approach or not is philosophical argument and I just happen to believe it's bad (and ugly) engineering - and in this case witnes the outcome, it cost Intel dearly in both monetary and PR terms.