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by thesz
1493 days ago
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Contemporary intermodule designs are pipelined and message-oriented exactly because it is hard to predict difference in signal path length for long paths. I am talking about high speed buses from ARM, I think I read about them in 2016 or so. The same can be done with asynchronous designs, in more relaxed way. You said that asynchronous designs are less predictable in their use of power. Can you elaborate on that? |
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Sure, just ask these guys:
https://chronostech.com/technology
Chronos Link: A QDI Interconnect for Modern SoCs https://ieeexplore.ieee.org/document/9179196
It's compatible with TileLink, which is SiFive's Fabric. https://bar.eecs.berkeley.edu/projects/tilelink.html