[ajb]

Not sure if you are actually talking about clockless logic. Maybe you are talking about asynchrony at a higher level of granularity.

But in fact there was a company founded to make FPGAs based on clockless logic: Achronix. They found that their customers wanted to map clocked designes onto their FPGAs and don't make any noise about clockless anymore - possibly their designs still use it under the hood, possibly not.

[JaCaLet]

Yes clockless logic no handshaking

[xwa32]

Even the most trivial design will need some form of synchronization which implies handshaking of some kind.

Asynchronous design is a really interesting field where it's pretty easy to get wins at the circuit level, but it's much harder to win at the system level. Especially when you realize there is no rule that says the system needs only one clock domain, and the period of those domains doesn't actually have to be constant.

I highly recommend you spend some time with a recent overview in the field if you're serious about it. Here is a good one:

http://www.cs.columbia.edu/~nowick/nowick-singh-async-IEEE-D...

[gaudat]

What handshaking? Never heard of that before.