[thesz]

You forgot that clock delay is computed for worst-case register and combinational logic behavior, e.g., "99.9999% of all registers need this amount of time for signal to be stable before write", "99.9999% of this gate in real silicon will have this delay".

The chart I saw several years ago put about half of typical clock cycle delay into this "reserve time" part. I guess things did not change much since then.

[keikobadthebad]

It depends what you are doing but with async it's possible to synthesize SR latches that don't have these setup / hold and metastability problems, the output of the logic is directly strobes that set or reset the storage element.