[cumshitpiss]

"Fastest way to compute"

This isn't necessarily true, especially considering the architecture of an FPGA. You have no control over the routing of the circuit and you're extremely restricted by the tools (which have decades of work towards synchronous circuits). More often than not, a synchronous circuit will end up being faster and more practical (there's a lot of overhead for async as well).

Another issue is that a lot of fundamental asynchronous primitives like the muller C-element and latches aren't really feasible to implement on the fpga (easily). The C-element requires a feedback loop on the LUT which is really hard to constrain properly, and the tool will fight you for doing that.

There's a cryptography paper out there comparing a synchronous and asynchronous implementation of ciphers and the conclusion was that synchronous was easier to implement and had higher throughput

[xwa32]

There's a lot of interesting research out there as designers having been toying with asynchronous for decades.

For example this one sponsored by Intel where they put an asynchronous instruction length decoder into a Pentium.

https://my.eng.utah.edu/~kstevens/docs/rappid.pdf

They won on latency and power with comparable area. The issue that blocked it was DFT CAD and the ATE infrastructure doesn't exist for asynchronous designs.