| > choose how logical elements are interconnected On the RTL level, you can already do that with FPGAs. On the physical level, you can't do that with an asynchronous design either. > absence of clocks (less devices The clocks are still there physically and consume space, even if you don't use them. > no need to synchronize Synchronization becomes very easy when the clocks are aligned and the frequencies are multiples of each other. FPGAs have delay elements in the clock blocks to help with the alignment. > energy is used when and where the switching happens. There are several points of energy use:
* the clock network -- you are right about this. Does anyone know how much of the total energy use goes into the clock network?
* registers and downstream logic -- behaves the same, whether synchronously or asynchronously. A register that doesn't "flip" will not consume energy for that, and the downstream logic will not flip either.
* whatever the asynchronous logic needs for coordination -- don't forget that this is not for free. Analyze energy consumption first before jumping to conclusions or even measures. The whole energy topic reeks of premature optimization. |