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by brendangregg
1511 days ago
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Yes, getting PMCs enabled in VMs was just the start, I think the next hardware capabilities to enable are: - PEBS (Precise/Processor event based sampling, so that we can accurately get instruction pointers on PMC events)
- uncore PMCs (in a safe manner)
- LBR (last branch record, to aid stack walking)
- BTS (branch trace store, " ")
- Processor trace (for cycle traces)
Processor trace may be the final boss. We've got through level 1, PMCs, now onto PEBS and beyond. |
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Congrats on the job.