[kqbx]

Although I don't (yet) own a real FPGA, I recently started to learn Verilog and wanted to see if I could program one using only open-source tools. My first impression is that the tooling is too fragmented and the documentation is lacking. I still don't fully understand the relationships between the major projects - F4PGA (is this the same as SymbiFlow?), VTR, yosys, ABC.

Ultimately I figured out how to use yosys+nextpnr so if I ever decide to dive deeper into the FPGA world, I will probably get an iCE40.

Also, is there an open-source tool for post-routing simulation? AFAIK this requires SDF annotation support which iverilog doesn't have.

[jmrm]

AFAIK there is no similar experience between programs, and the only thing in common is the base code, because depending on how the device and the tooling is, you need not only to configure which device are going to be used and how this will be used, but also you might need to create/edit manually files to link some inputs, outputs, and clocks.

In this matter my "real" experiences using Xilinx ISE and Xilinx Vivado, and the "virtual" ones are using the Mentor Graphics ModelSim, all of them using VHDL. Maybe in other suites, or using SystemC or SystemVerilog there are other experience, but I understand something so niche like this have this kind of quirks.