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by TomVDB 1518 days ago
How is that a relevant comment in a discussion about ASIC design?

I hope you don't have the idea that chip routing is done manually.

2 comments

IIRC, Place & Route is a known NP complete problem. In this regard, autorouters (whether IC or PCB) can benefit from "better" heuristics -- i.e. it's an optimization problem where AI can help.
PCB routing is generally considered a much harder problem. There are a bunch of reasons that add up, but one of them is almost certainly that a PCB is supposed to look good too. The routing on an IC is total chaos (which actually reduces crosstalk issues), but nobody will ever notice.
That's an interesting point

PCBs "look good" because of different production contraints (and I guess because you're mostly connecting tight-timed busses together)

In ICs you're doing the above but also pulling signals from 10 different places together.

So here's my autorouter first-guess analog computer design:

On a basketball court create a pile of metal plates with bar codes and hooks, each one represents a gate, robot uses rubber bands of sizes vaguely representing timing budget from synthesis to hook the gates together. Robot picks up the whole thing using rubber bands representing the external ports and gives the whole thing a few shakes. Puts it all back down, goes over each metal plate and reads the bar code and resting position - that's your initial routing guess - anneal from there

What you've described is actually for placement, not routing, and is in fact a good analogy for the first step in many placement algorithms.

Interestingly, placement is much harder than routing from a complexity theory point of view (specifically, there are fairly strong inapproximability results for placement-style problems).

true - most chip tools I've used for layout do both place and route (and iterate, moving std cells apart to create routing resources) so I've always sort of thought of place&route as a single thing (though I've also interrupted it before initial routing to do scan insertion)
Are the analog parts (current nitrist etc) autorouted now?

I worked on MCU layout around 2011, and only the digital logic was autorouted/placed.

My comment is in the context of this topic: large digital ASICs with billions of wires, where the only analog parts are PLLs, DLLs, and digital IOs.