[tsmi]

I do totally agree with the comment, and even upvoted it, but in some sense an HDL does 'want to be procedural'. For example:

   Procedure to make brick wall:
   For brick in wheel-barrow do
     To brick, apply mortar, place it, pound it with trowel

(Apologies to all masons. I think you can tell my training is electrical engineering.)

I've thought for some time that the main problem with Verilog is that it looks really close, visually, to C and that gives people the wrong impression.

[bsder]

Except that's not how you do it.

My go-to example for this is the Carry-skip Adder. (https://en.wikipedia.org/wiki/Carry-skip_adder)

Things are happening simultaneously in time and space. The ripples are happening while the skips are happening. The skips go stable because the ripple goes stable or the carry will skip so the ripple has "extra time" to go stable.

This is the simplest add faster than naive ripple carry. Note that it has no clocks. This is a purely combinatoric problem. And most "digital designers" will get it wrong.

Hardware design is NOT software design. Good digital designers are always thinking about how to interleave things in time and space like this.