[tsomctl]

I've been reverse engineering a modern ABS control module. It has 2 cores, and they are separate CPU's with their own memory (although one cpu can access the RAM of the other CPU) and role. One reads/writes the CAN bus and does verification on that data, the other CPU is the one that monitors wheel speed sensors and determines when to control the solenoid valves. There is a cleanly defined area where data is copied from one CPU to the other.