[tyingq]

Driving LED matrix displays is a good example, since they require good adherance to timing on the output signal. Especially at high refresh rates. There's lots of hobby projects that get away with just using the CPU, but you're throwing a lot of horsepower at something a cheap CPLD could handle fine. There's also solutions like using the "PRU" in a Beaglebone to drive the display...the PRU is basically a microcontroller that can share memory with the CPU, but can work in a more real-time fashion.

So it's not always raw speed, per se, but anything that's sensitive to timing. Linux on a PI can be busy doing something else and miss a critical time to have output (or read) something. An FPGA based solution is working with known loop/io/etc times that don't change.

[marktangotango]

That's interesting, looks like the PRU is built into the AM3358 SOC, is that correct?

[tyingq]

Yes, I believe it's in all (most?) of the products within the "Sitara" line, or at least AM33XX models.

Lowrisc.org also has a similar plan for what they call "minion cores" in their RISCV based product, whenever that happens. Some NXP processors also have something called an "eTPU" that seems similar.