[mlyle]

> With design randomization, you can make it hard to detect patterns like that. Think things like randomizing the polarity of each bit line going in/out of RAM. Again, the point is the backdoor has to work with any design, and this opens up a wide range of mitigations that you can implement at that stage, that make it a lot less practical.

This doesn't really work-- assume the adversary has your design. Then they can appropriately figure out how to get the right bits across some part of it that matters.

[marcan_42]

The idea for Precursor is that every user runs a different random build of the design.

[mlyle]

The only thing that seems to be randomized in building precursor is the P&R seed.

https://github.com/betrusted-io/betrusted-soc/blob/main/betr...

That prevents attacks where you have a known place on the FPGA is naughty, but not when you have a lot of elements that are naughty on certain input.

It doesn't even really protect against known-naughty-place: there's not infinite freedom on P&R with fixed I/O locations.

[marcan_42]

Right now, sure, but there are more mitigations that can be added. This is an area ripe for research. The idea is that this kind of device and approach allows for further research, which can benefit users in the future since it's soft logic.

Again, I'm not saying this is a silver bullet, I'm saying it's an interesting approach and can claim to at least mitigate the risk of silicon backdoors by making them harder to pull off, which is more than can be said of the typical hard logic approach.