[zaidhaan]

As someone without a background in EE I find it fascinating how we are able to build hardware that operates and deals with data at high speeds that it needs to be debugged using statistical analysis.

How is it even possible to have correctly functioning circuits at such high speeds? I'm guessing at the very bottom of the Phy layer there several transistors switching at incredibly fast speeds. I understand that these transistors have several parameters such as their delay, rise, and fall time. Things most certainly don't happen instantaneously, a few logic ICs I played with also have a propagation delay time specified in their data sheets lasting a few nanoseconds.

Take the deserializer for an example, happening at 16Gb/s, which if I understand correctly equates to 1 bit every 62.5ps (0.0625ns). How does any circuit affected by the parameters I just talked about handle signals at such high speeds?

(Please go easy on me, I know some of my assumptions are probably wrong or oversimplified but I would love to learn more)

[jjoonathan]

Select 30nm CMOS processes already had fT (frequency at which transistor no longer has gain) of 300GHz, so the component-level limits are probably flirting with THz by now. Of course, you need to knock off an order of magnitude to build useful comparators/etc out of those, and that gives you... 100GHz, right about what we see on those high speed SerDes :)

One more thing: CMOS historically wasn't the fastest logic family. Bipolar ECL was faster, but it burned a ton of idle current, so it ran into power limitation long before CMOS.

In either case, thermal limits prevent you from using these speeds across the whole chip, but just because your thermal budget can't afford 10,000,000,000 speed demons doesn't mean it can't afford 1000 of them in a few SerDes :)

But yeah, decades of Moore's law have not gone to waste, and those discrete logic chips are frozen in time. It's a neat reminder of how far we have come!