[brucehoult]

It is physically and logically impossible for any one practical ISA to optimally cover every one of the thousands of highly specialised application areas.

You, apparently, really really care about arbitrary-precision adds.

RISC-V is a general purpose ISA. It can do any computing task, just perhaps not optimally.

How non-optimal is it for arbitrary-precision adds? Or, more importantly, for the overall application that is a part of. No one who has raised this as a concern has shown any actual numbers. In fact they don't even show the actual loop doing the arbitrary-precision add, with loop control instructions, loads and stores. All they show is that a single "add-with-carry" instruction in some other ISAs translates to several instructions in RISC-V.

The problem, if any, in your application area can be solved by adding a single custom instruction to the ISA.

That doesn't sound like something fundamentally wrong with the ISA. Especially when that ISA is designed from the start to be extensible by users via adding custom instructions.

[ddingus]

We will see. I think flags in general have enough advantages that the chip really should have them.

And it's not just an arbitrary Precision. There's a variety of constructs that will be longer.

And hey, it's not like I'm anti. We'll see where it all goes, and if it really does shake out like the proponents say, this will just be an academic matter.

I would rather some really good instructions be part of the base set just so they have broad coverage. The whole just add a rando instruction idea doesn't appeal to me at all.